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1998.6.18 Ver.A
MITSUBISHI LSIs
PRELIMINARY
Notice: This is not a final specification. Some parametric limits are subject to change.
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
DESCRIPTION The M5M564R16D is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB.
ADDRESS INPUTS CHIP SELECT INPUTS DATA INPUTS/ OUTPUTS
PIN CONFIGURATION (TOP VIEW)
FEATURES
M5M564R16DJ,TP-10 ... 10ns(max) M5M564R16DJ,TP-12 ... 12ns(max) M5M564R16DJ,TP-15 ... 15ns(max) *Low power dissipation Active .................. 363mW(typ) *Single +3.3V power supply *Fully static operation : No clocks, No refresh *Common data I/O *Easy memory expansion by S *Three-state outputs : OR-tie capability *OE prevents data contention in the I/O bus *Directly TTL compatible : All inputs and outputs *Separate control of lower and upper bytes by LB and UB *Fast access time
A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4
1 2 3 4 5 6
44 43 42 41 40 39
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
(3.3V) VCC (0V) GND
DATA INPUTS/ OUTPUTS WRITE CONTROL INPUT ADDRESS INPUTS
A15 A14 ADDRESS INPUTS A13 OUTPUT ENABLE OE INPUT UB BYTE CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V)
M5M564R16DJ,TP
VCC (3.3V)
DQ12 DQ11 DQ10 DQ9 N.C A12 A11 A10 A9 N.C
DATA INPUTS/ OUTPUTS
DQ5 DQ6 DQ7 DQ8 W A5 A6 A7 A8 N.C
ADDRESS INPUTS
Outline 44P0K(J) 44P3W-H(TP)
APPLICATION
High-speed memory system
PACKAGE
M5M564R16DJ M5M564R16DTP : 44pin 400mil SOJ : 44pin 400mil TSOP(II)
FUNCTION
The operation mode of the M5M564R16D is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time.
MITSUBISHI ELECTRIC
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION TABLE
S L L L L L L L L H W H H H L L L H X X OE L L L X X X H X X LB L H L L H L X H X UB L L H L L H X H X Mode Read cycle All Bytes Read cycle Upper Bytes Read cycle Lower Bytes Write cycle All Bytes Write cycle Upper Bytes Write cycle Lower Bytes Output disable Non selection DQ1~8 D OUT High-impedance D
OUT
DQ9~16 D OUT D OUT High-impedance D IN D IN High-impedance High-impedance High-impedance
Icc Active Active Active Active Active Active Active Stand by
D IN High-impedance D IN High-impedance High-impedance
BLOCK DIAGRAM
ADDRESS INPUTS
A0 A1 A2 A3 A4 A5 A6 A7 A8 S W OE UB LB
ROW INPUT BUFFERS
3 4 5 18 19 20 21
ROW ADDRESS DECODERS
1 2
18
512
2048
DATA INPUT BUFFERS
MEMORY ARRAY 512 ROWS 2048 COLUMNS
7 8 9 10 13 14 15 16
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
OUTPUT BUFFERS
DATA INPUTS/ OUTPUTS
OUTPUT BUFFERS
CHIP SELECT INPUTS WRITE CONTROL INPUT OUTPUT ENABLE INPUT UPPER BYTE CONTROL INPUTS LOWER BYTE CONTROL INPUTS
6 17
COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS
14
29 30 31 32 35 36 37 38
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16
DATA INPUTS/ OUTPUTS
41
COLUMN INPUT BUFFERS
DATA INPUT BUFFERS 11 33 12 34
40
VCC
(3.3V)
39 24 25 26 27 42 43 44
GND (0V)
A9 A10 A11 A12 A13 A14 A15
ADDRESS INPUTS
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol V cc VI VO Parameter Supply voltage Input voltage Conditions With respect to GND Ta=25C Ratings - 2.0*~ 4.6 - 2.0*~ Vcc+0.5 - 2.0*~ Vcc 1000 0 ~ 70 - 10 ~ 85 - 65 ~ 150 Unit V V V mW C C C
Output voltage Power dissipation Pd Operating temperature T opr Tstg(bias) Storage temperature(bias) Tstg Storage temperature
*Pulse width 5ns, In case of DC: - 0.5V
DC ELECTRICAL CHARACTERISTICS
Symbol VIH VIL VOH VOL II IOZ Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current in off-state Active supply current (TTL level)
(Ta=0~70C, Vcc=3.3V Condition
+10% -5% ,unless
otherwise noted) Min 2.0 2.4 0.4 2 2 Limits Typ Max Vcc+0.3 0.8 Unit V V V V uA uA
IOH = - 4mA IOL= 8mA V I = 0 ~ Vcc VI (S)= VIH VO= 0 ~ Vcc VI (S)= VIL other inputs V IH or VIL Output-open(duty 100%) AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC AC(10ns cycle) AC(12ns cycle) AC(15ns cycle) DC
I CC1
110
I CC2
Stand-by supply current (TTL level) Stand-by current (MOS level)
VI (S)= VIH VI (S)= Vcc - 0.2V other inputs VI0.2V or VIVcc - 0.2V
200 195 190 140 70 65 60 40 10
mA
mA
I CC3
mA
Note 1: Direction for current flowing into an IC is positive (no mark).
CAPACITANCE
Symbol CI CO
(Ta=0~70C , Vcc=3.3V Parameter
+10% -5% ,unless
otherwise noted) Test Condition Min Limit Typ Max 6 8 Unit pF pF
Input capacitance Output capacitance
VI =GND,Vi =25mVrms,f=1MHz Vo =GND,Vo =25mVrms,f=1MHz
Note 2: CI,CO are periodically sampled and are not 100% tested.
AC ELECTRICAL CHARACTERISTICS (Ta= 0~70 C
(1) MEASUREMENT CONDITION
Input pulse levels ................................... VIH=3.0V,VIL=0.0V Input rise and fall time ................................................... 3ns Input timing reference levels ...................... VIH=1.5V,VIL=1.5V Output timing reference levels ................ VOH=1.5V, VOL=1.5V Output loads ....................................................... Fig1 ,Fig2
OUTPUT
,VCC=3.3V
Z0=50
+10% -5% ,unless
otherwise noted)
5.0V 480
DQ RL=50 VL=1.5V Fig.1 Output load
DQ 255 5pF Including scope and JIG
(
)
Fig.2 Output load for t en, t dis
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
READ CYCLE
Limits
Symbol Parameter M5M564R16D-10 M5M564R16D-12 M5M564R16D-15 Unit
Min tCR ta(A) ta(S) ta(OE) ta(B) tdis(S) tdis(OE) tdis(B) ten(S) ten(OE) ten(B) tv(A) tPU tPD
Read cycle time Address access time Chip select access time Output enable access time LB,UB access time Output disable time after S high Output disable time after OE high Output disable time after LB,UB high Output enable time after S low Output enable time after OE low Output enable time after LB,UB low Data valid time after address change Power-up time after chip selection Power down time after chip selection
Max 10 10 5
Min 12
Max 12 12 6
Min 15
Max ns 15 15 7 ns ns ns ns ns ns ns ns ns ns ns ns 15 ns
10
0 0 0 4 3 3 4 0
5 5 5 5
0 0 0 4 3 3 4 0
6 6 6 6
0 0 0 4 3 3 4 0
7 7 7 7
10
12
Write cycle
Limits
Symbol Parameter M5M564R16D-10 M5M564R16D-12 M5M564R16D-15 Unit
Min tCW tw(W) tsu(B) tsu(A)1 tsu(A)2 tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ten(B) tsu(A-WH) tsu(A-SH) tsu(A-BH)
Write cycle time Write pulse width LB,UB setup time Address setup time(W) Address setup time(S) Chip select setup time Data setup time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Output enable time after LB,UB low Address to W High Address to S High Address to LB,UB High
Max
Min 12 10 10 0 0 10 6 0 0 0 0 0 0 0 10 10 10
Max
Min 15 12 12 0 0 12 7 0 0 0 0 0 0 0 12 12 12
Max ns ns ns ns ns ns ns ns 7 7 ns ns ns ns ns ns ns ns ns
10 9 9 0 0 9 5 0 0 0 0 0 0 0 9 9 9
5 5
6 6
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS Read cycle 1 A 0~15
VIH VIL
t CR
ta(A) tv(A) tv(A)
UNKNOWN DATA VALID PREVIOUS DATA VALID
DQ1~16
VOH VOL W=H S=L OE=L
LB=L UB=L
Read cycle 2 (Note 3)
t
CR
S
VIH VIL
ta(S) ten(S)
(Note 4)
tdis(S)
(Note 4)
DQ1~16
VOH VOL
UNKNOWN
DATA VALID
tPU
tPD
50% 50%
Icc
ICC1 ICC2 W=H UB=L
OE=L LB=L
Note 3. Addresses valid prior to or coincident with S transition low. 4. Transition is measured 500mv from steady state voltage with specified loading in Figure 2.
Read cycle 3 (Note 5) OE
VIH VIL
t CR
ta(OE)
(Note 4)
tdis(OE)
(Note 4)
ten(OE)
UNKNOWN DATA VALID
DQ1~16
VOH VOL W=H S=L UB=L LB=L
Note 5. Addresses and S valid prior to OE transition low by (ta(A)-ta(OE)), (ta(S)-ta(OE))
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
Read cycle 4 (Note 6) UB,LB
VIH VIL
t CR
ta(B)
(Note 4)
tdis(B)
(Note 4)
ten(B)
UNKNOWN DATA VALID
DQ1~16
VOH VOL W=H S=L OE=L
Note 6. Addresses , S and OE valid prior to LB,UB transition low by (ta(A)-ta(B)), (ta(S)-ta(B)), (ta(OE)-ta(B)).
Write cycle (W control mode)
t CW
A 0~15 S
VIH VIL VIH VIL
tsu(S)
(Note 7) (Note 7)
tsu(A-WH)
OE
VIH VIL
tsu(A)
tw(W)
trec(W)
W
VIH VIL
tsu(B)
LB,UB
VIH VIL
(Note 7)
(Note 7)
tsu(D) th(D)
DQ1~16
(Input Data)
VIH VIL
DATA STABLE
tdis(W) (Note 4) tdis(OE)
ten(OE) (Note 4) ten(W)
DQ1~16
(Output Data)
VOH VOL
Hi-Z
Note 7: Hatching indicates the state is don't care. 8: When the falling edge of W is simultaneous or prior to the falling edge of S, the output is maintained in the high impedance. 9: ten,tdis are periodically sampled and are not 100% tested.
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MITSUBISHI LSIs
M5M564R16DJ,TP-10,-12,-15
1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle(S control)
t CW
A 0~15
VIH VIL
tsu(A)
tsu(A-SH) tsu(S)
trec(W)
S W
VIH VIL
tw(W)
VIH VIL
(Note 6) (Note 6)
tsu(B)
LB,UB
VIH VIL
(Note 6) (Note 6)
tsu(D)
th(D)
DQ1~16
(Input Data)
VIH VIL
(Note 4)
DATA STABLE
tdis(W) ten(B) ten(S)
(Note 4)
DQ1~16
(Output Data)
VOH VOL
Hi-Z
(Note 8)
Write cycle(LB,UB control)
t CW
A 0~15
VIH VIL
tsu(S)
S W
VIH VIL
(Note 6) (Note 6)
tw(W)
VIH VIL
(Note 6)
tsu(A)
tsu(A-BH) tsu(B)
(Note 6)
trec(W)
LB,UB
VIH VIL
tsu(D)
th(D)
DQ1~16
(Input Data)
VIH VIL
DATA STABLE
tdis(W)
(Note 4)
(Note 4)
DQ1~16
(Output Data)
VOH VOL
ten(B)
ten(S)
Hi-Z
(Note 8)
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